@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: MO111 :"c:\users\test\desktop\calculator_fpga_mico8\source\cap1298_top.v":43:14:43:26|Tristate driver scl_out_1 (in view: work.cap1298_top(verilog)) on net scl_out_1 (in view: work.cap1298_top(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\test\desktop\calculator_fpga_mico8\source\cap1298_top.v":43:14:43:26|Tristate driver scl_out_2 (in view: work.cap1298_top(verilog)) on net scl_out_2 (in view: work.cap1298_top(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\test\desktop\calculator_fpga_mico8\source\calculator.v":42:5:42:18|Tristate driver lcd_data_out (in view: work.calculator(verilog)) on net lcd_data_out (in view: work.calculator(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\test\desktop\calculator_fpga_mico8\source\calculator.v":42:20:42:33|Tristate driver lcd_clk_out (in view: work.calculator(verilog)) on net lcd_clk_out (in view: work.calculator(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\test\desktop\calculator_fpga_mico8\source\calculator.v":15:8:15:17|Tristate driver lcd_dc_out (in view: work.calculator(verilog)) on net lcd_dc_out (in view: work.calculator(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\test\desktop\calculator_fpga_mico8\source\calculator.v":14:8:14:17|Tristate driver lcd_cs_out (in view: work.calculator(verilog)) on net lcd_cs_out (in view: work.calculator(verilog)) has its enable tied to GND.
@N: MO111 :"c:\users\test\desktop\calculator_fpga_mico8\source\calculator.v":13:8:13:18|Tristate driver lcd_rst_out (in view: work.calculator(verilog)) on net lcd_rst_out (in view: work.calculator(verilog)) has its enable tied to GND.
@N: MO111 :|Tristate driver scl_out_t[1] (in view: work.calculator(verilog)) on net scl_out[1] (in view: work.calculator(verilog)) has its enable tied to GND.
@N: MO111 :|Tristate driver scl_out_t[2] (in view: work.calculator(verilog)) on net scl_out[2] (in view: work.calculator(verilog)) has its enable tied to GND.
@N: MF236 :"c:\users\test\desktop\calculator_fpga_mico8\source\compute.v":136:37:136:52|Generating a type div divider 
@N: FX493 |Applying initial value "0000000" on instance compute_u.data_out_reg[6:0] 
@N: FX493 |Applying initial value "000" on instance compute_u.operate_reg[2:0] 
@N: FX493 |Applying initial value "00000000" on instance cap1298_top_u.cap1298_i2c_u1.keys_status[7:0] 
@N: FX493 |Applying initial value "00" on instance cap1298_top_u.cap1298_i2c_u1.state_back[1:0] 
@N: FX493 |Applying initial value "000000" on instance cap1298_top_u.operate_status[6:1] 
@N: BN362 :"c:\users\test\desktop\calculator_fpga_mico8\source\uart_tx.v":50:0:50:5|Removing sequential instance tx_data_r[8] (in view: work.Uart_Tx(verilog)) because it does not drive other instances.
@N: BN362 :"c:\users\test\desktop\calculator_fpga_mico8\source\uart_tx.v":50:0:50:5|Removing sequential instance Uart_Tx_u.tx_data_r[7] (in view: work.calculator(verilog)) because it does not drive other instances.
@N: FA113 :"c:\users\test\desktop\calculator_fpga_mico8\source\compute.v":53:8:53:11|Pipelining module un1_value1[11:0]. For more information, search for "pipelining" in Online Help.
@N: MF169 :"c:\users\test\desktop\calculator_fpga_mico8\source\compute.v":35:0:35:5|Pushed in register value1[15:0].
@N: MF169 :"c:\users\test\desktop\calculator_fpga_mico8\source\compute.v":35:0:35:5|Pushed in register value2[15:0].
@N: MF169 :"c:\users\test\desktop\calculator_fpga_mico8\source\compute.v":35:0:35:5|Pushed in register cal_number[3:0].
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@N: MO111 :"c:\users\test\desktop\calculator_fpga_mico8\source\calculator.v":5:15:5:21|Tristate driver scl_out_obuft_1_.un1[0] (in view: work.calculator(verilog)) on net scl_out[1] (in view: work.calculator(verilog)) has its enable tied to GND.
@N: FO126 :"c:\users\test\desktop\calculator_fpga_mico8\source\compute.v":35:0:35:5|Generating RAM compute_u.bcd_data_reg[3:0]
@N: MT611 :|Automatically generated clock cap1298_i2c|clk_200khz_derived_clock is not used and is being removed
@N: FX1056 |Writing EDF file: C:\Users\TEST\Desktop\calculator_fpga_mico8\impl1\calculator_impl1.edi
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
